Four transistors static-random-access-memory cell

ABSTRACT

A four-transistors SRAM cell, which could be viewed as at least including two word line terminals, comprises following elements: first word line terminal, second word line terminal, first bit line terminal, second bit line terminal, first transistor, second transistor, third transistor, and fourth transistor. Whereby, gate of first transistor is coupled to first word line terminal and source of first transistor is coupled to the first bit line terminal, gate of second transistor is coupled to second word line terminal and source of second transistor is coupled to second bit line terminal, source of third transistor is coupled to drain of first transistor and gate of third transistor is coupled to drain of second transistor, source of fourth transistor is coupled to drain of second transistor and gate of fourth transistor is coupled to drain of first transistor. Significantly, one essentially characteristic of the memory cell is two word line terminals are used to control state of two independent transistors separately.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates generally to a four-transistorsstatic-random-access-memory (SRAM) memory cell that is suitable forapply to the lower power product, that has a reduced size as comparedwith conventional SRAM cells, or both.

[0003] 2. Description of the Prior Art

[0004] To meet customer demand for small size and low power products,manufacturers are producing newer integrated circuits (ICs) that operatewith lower supply voltages and that include smaller internal subcircuitssuch as memory cells. Many ICs, such as memory circuits or othercircuits such as microprocessors that include onboard memory, includeone or more SRAM cells for data storage. SRAMs cells are popular becausethey operate at a higher speed than dynamic random-access-memory (DRAM)cells, and as long as they are powered, they can store dataindefinitely, unlike DRAM cells, which must be periodically refreshed.

[0005] Conventional structure of SRAM cell is a six-transistors SRAMcell, which means six transistors are used to form a SRAM cell. Ingeneral, advantages of six-transistors SRAM cell at least include highspeed and possibility of low supply voltage. By unfortunately, oneunavoidable disadvantage is that area of six-transistor SRAM cell islarge. Clearly, when size of semiconductor device is continuallydecreased, the disadvantage is more serious and it is desired toovercome the disadvantage by either improving structure ofsix-transistors SRAM cell or providing a new SRAM cell.

[0006] One way to reduce area of six-transistors SRAM cell is to makestructure to be three-dimensional. However, to solidity structure ofsix-transistors SRAM cell also complicates relative fabrication andconfiguration of six-transistors SRAM cell. In other words, this way isnot an efficient way.

[0007] Another popular way to reduce area of six-transistors SRAM cellis application of four-transistors SRAM. Although there are numerousvarieties of four-transistors SRAM cell, the basic structure offour-transistors SRAM cell can be divided into two access transistorsand two pull-down transistors. Herein, as usual, one access transistorand one pull-down transistor are used to storage data, another accesstransistor and another pull-down transistor are used to controlreading/writing processes. Clearly, owing to number of used transistoris decreased, occupied area of four-transistors SRAM cell is less thansix-transistors SRAM cell. Thus, four-transistors SRAM cell is moresuitable for ICs whenever sizes of ICs are reduced, evenfour-transistors also meets some disadvantages such as higher off-stateleakage current of PMOS. More introduction of four-transistors SRAM cellcan be provided by referring to U.S. Pat. Nos. 5,943,269, 6,091,628,6,044,011, 6,011,726, 5,751,044 and so on.

[0008] One ordinary circuit diagram of four-transistor SRAM cell isshown in FIG. 1. The four-transistor SRAM cell, which is a loadlessfour-transistors SRAM cell, comprises first transistor 11, secondtransistor 12, third transistor 13, fourth transistor 14, first wordline terminal 15, second word line terminal 16, first bit line terminal17 and second bit line terminal 18. In detail, source of firsttransistor 11 is coupled to first bit line terminal 17, gate of firsttransistor 11 coupled to first word line terminal 15, drain of firsttransistor 11 is coupled to gate of fourth terminal 14, source of secondtransistor 12 is coupled to second bit line terminal 18, gate of secondtransistor is coupled to second word line terminal 16, drain of secondtransistor 12 is coupled to gate to third transistor 13. More over,drain of fourth transistor 14 and drain of third transistor 13 arecoupled to a common voltage point 19, such as electrical zero point,each of both first bit line terminal 17 and second bit line terminal 18is coupled to a corresponding bit line, and both first word lineterminal 15 and second word line terminal 16 are coupled to the sameword line.

[0009] Because leakage current of first transistor 11 and leakagecurrent of second transistor 12 are not absolute zero, especially whenfirst transistor 11/second transistor 12 are P-type transistor. Anunavoidable shortage is that because first word line terminal 15 andsecond word line terminal 16 by same word line, third transistor 13 isturn on by leakage current of second transistor 12 whenever both firsttransistor 11 and second transistor 12 are not totally turn off. Thus,whenever current is sent to first bit line terminal 17 (means data isstoraged), owing to both first transistor 11 and third transistor 13 arenot totally turn off now, current continually flow through firsttransistor 11 and third transistor into common voltage point 19.Significantly, continuous flow of current requires continuous supply ofcurrent, then stand-by current of the four-transistor SRAM cell is notnegligible and the four-transistor SRAM cell is less suitable for lowpower product.

[0010] Therefore, although four-transistor SRAM is physically smallerand is suitable for some ICs that include smaller internal subcircuits,it still is not enough suitable for operation at low supply power. Then,improvement of four-transistor SRAM is desired to let it is suitable forlow power product.

SUMMARY OF THE INVENTION

[0011] One main object of the invention is to present a four-transistorsSRAM cell which is suitable for low power product.

[0012] Another important object of the invention is to present afour-transistors SRAM cell which is easy to be produced, especially thedifferences between the present four-transistors SRAM cell and otherwell-known four-transistors SRAM cell are not too large to letfabrication of the present four-transistors SRAM cell is stronglydifferent from fabrication of the well-known four-transistors SRAM cell.

[0013] Still an essential object of the invention is to present afour-transistors SRAM cell by limiting circuit diagram of the presentfour-transistors SRAM cell but not limiting structure of the presentfour-transistors SRAM cell. In other words, there are various structuresof the present four-transistors SRAM cell.

[0014] One embodiment of the invention is a memory cell, a fourthtransistor SRAM cell, which comprises following elements: first wordline terminal, second word line terminal, first bit line terminal,second bit line terminal, first transistor, second transistor, thirdtransistor, and fourth transistor. Whereby, gate of first transistor iscoupled to first word line terminal and source of first transistor iscoupled to the first bit line terminal, gate of second transistor iscoupled to second word line terminal and source of second transistor iscoupled to second bit line terminal, source of third transistor iscoupled to drain of first transistor and gate of third transistor iscoupled to drain of second transistor, source of fourth transistor iscoupled to drain of second transistor and gate of fourth transistor iscoupled to drain of first transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] A more complete appreciation and many of the attendant advantagesthereof will be readily obtained as the same becomes better understoodby reference to the following detailed description when considered inconnection with the accompanying drawings.

[0016]FIG. 1 is a sketch map about circuit diagram of a conventionalfour-transistors SRAM cell;

[0017]FIG. 2 is a sketch map about circuit diagram of a four-transistorSRAM cell according to an embodiment of the invention; and

[0018]FIG. 3A and FIG. 3B show sketch maps about two possibleconfiguration of the embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0019] One preferred embodiment is a memory cell, a four-transistorsSRAM cell. As shown in FIG. 2, circuit diagram of the embodimentcomprises: first word line terminal 21, second word line terminal 22,first bit line terminal 23, second bit line terminal 24, firsttransistor 25, second transistor 26, third transistor 27 and fourthtransistor 28. Wherein, each word line terminal (21, 22) is coupled to aword line, and each bit lint terminal (23, 24) is coupled to a bit line.Clearly, basic elements of the present four-transistors SRAM cell issimilar to well-known four-transistors SRAM cell. Then, the differencesbetween the present four-transistors SRAM cell and well-knownfour-transistors SRAM cell are functions and relations of these basicelements.

[0020] As shown in FIG. 2, gate of first transistor 25 is coupled tofirst word line terminal 21 and source of first transistor 25 is coupledto first bit line terminal 23, gate of second transistor 26 is coupledto second word line terminal 22 and source of second transistor 26 iscoupled to second bit line terminal 24, source of third transistor 27 iscoupled to drain of first transistor 25 and gate of third transistor 27is coupled to drain of second transistor 26, source of fourth transistor28 is coupled to drain of second transistor 26 and gate of said fourth28 transistor is coupled to drain of first transistor 25. Moreover,first word line terminal 21 and second word line terminal 22 arecontrolled separately, which means voltage of first word line terminal21 could be different than, and be controlled separately, voltage ofsecond word line terminal 22. Besides, first bit line terminal 23 andsecond bit line terminal 24 also are coupled to corresponding bit lines.

[0021] By compare FIG. 2 with FIG. 1, it is crystal-clear that the maindifference between the present four-transistors SRAM cell and well-knownfour-transistors SRAM cell is the relations between SRAM cell and wordline(s). For well-know four-transistors SRAM cell, first transistor 11and second transistor 12 are coupled to the same word line; but for thepresent four-transistors SRAM cell, first transistor 25 and secondtransistor 26 are coupled to different word lines.

[0022] Significantly, gate voltage of first transistor 25 and gatevoltage of second transistor 26 can be adjusted separately. Thus, whenfirst transistor 25 and third transistor 27 are adjusted to be used tostore data, although gate voltage of first transistor 25 can not be tooextreme to affect operation of circuit which provided by both firsttransistor 25 and third transistor 27, gate voltage of second transistor26 can be enough adjusted to let almost no leakage current is existent.In other words, by properly adjusting gate voltage of second transistor26, third transistor 23 will not be turn on by leakage current of secondtransistor 26, and then quantity of stand-by current is reduced for lessstand-by current is required to compensate lost current of thirdtransistor 27.

[0023] Further, for most of case, and also for increasing of the presentfour-transistors SRAM cell, both first transistor 25 and secondtransistor 26 usually are P-type transistor, and both third transistor27 and fourth transistor 28 are N-type transistor. Besides, both drainof third transistor 27 and drain of fourth transistor 28 is coupled to acommon electric point 29, such as an electrical zero point. For apractical example, voltage of second word line terminal 22 is higherthan voltage of first word line terminal 21 whenever the present memorycell is in stand-by and both second transistor 26 and first transistor25 are P-type transistors. In other words, voltage of second transistor26 is adjusted to reduce leakage current of second transistor 26.

[0024] Accordingly, the present four-transistor SRAM cell is suitablefor low power product for it requires less stand-by current. Besides,owing to two word lines can be provided by multilevel metallizationprocess, configuration of the present four-transistor SRAM cell can beessentially similar to that of well-known four-transistor, and thenoccupied area of the present four-transistors SRAM cell still is small.However, it should be emphasized that the present invention is focusedon circuit of the present four-transistors SRAM cell but not thepractical configuration of the memory cell. Any memory cell, anyfour-transistors SRAM cell, has a circuit-diagram as FIG. 2 shows is thesubject, claimed range, of the present invention.

[0025] For showing some possible practical configurations, FIG. 3A andFIG. 3B briefly and qualitatively illustrate two examples. The Exampleshown in FIG. 3A at least includes fourth gates and three individualmulti-doped regions where each is formed by a series of doped regions.Moreover, detail combination of any multi-doped region is different fromthat of other multi-doped region. Obviously, part of first multi-dopedregion 31, first gate 32 and part of second multi-doped region forms 33fourth transistor, part of first multi-doped region 31, second gate 34and part of second multi-doped region 33 forms third transistor, part ofsecond multi-doped region 33 and third gate 35 forms second transistor,third multi-doped region 36 and fourth gate 37 forms first transistor.Moreover, third gate 35 is independent on fourth gate 37, and thenmultilevel metallization process is used to avoid third gate 35 iscoupled with (or is connected to) fourth gate 37.

[0026]FIG. 3B shows another possible configuration of the presentfour-transistors SRAM cell. Herein, essential elements are firstmulti-doped region 41, second multi-doped region 42, first gate 43,second gate 44, third gate 45 and fourth gate 46. Certainly, detailcombination of any multi-doped region is different from that of othermulti-doped region, and also is different form that of FIG. 3A. Herein,part of first multi-doped region 41 and first gate 43 forms secondtransistor, part of second multi-doped region 42 and second gate 44forms first transistor, part of first multi-doped region 41, part ofsecond multi-doped region 42 and third gate 45 forms third transistor,part of first multi-doped region 41, part of second multi-doped region42 and fourth gate 46 forms fourth transistor. Further, because firstgate 43 and fourth gate 46 are located in opposite part of the cell, andalso because that first gate 43 is parallel to fourth gate 46, it ispossible that the configuration can be achieved without application ofmultilevel metallization process. Besides, first multi-doped region 41comprises a N-type doped region and a P-type doped region, secondmulti-doped region 41 comprises a N-type doped region and a P-type dopedregion.

[0027] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purpose ofillustration, various modification may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

What is claimed is:
 1. A four-transistors SRAM cell, comprising: a firstword line terminal which is coupled to a first word line; a second wordline terminal which is coupled to second word line, wherein said firstword line terminal and said second word line terminal are controlledseparately; a first bit line terminal which is coupled to a firstbit-line; a second bit line terminal which is coupled to a secondbit-line; a first transistor, wherein the gate of said first transistoris coupled to said first word line terminal and the source of said firsttransistor is coupled to said first bit line terminal; a secondtransistor, wherein the gate of said second transistor is coupled tosaid second word line terminal and the source of said second transistoris coupled to said second bit line terminal; a third transistor, whereinthe source of said third transistor is coupled to the drain of saidfirst transistor and the gate of said third transistor is coupled to thedrain of said second transistor; and a fourth transistor, wherein thesource of said fourth transistor is coupled to the drain of said secondtransistor and the gate of said fourth transistor is coupled to thedrain of said first transistor.
 2. The cell of claim 1, wherein bothsaid first transistor and said second transistor are P-type transistor.3. The cell of claim 2, wherein both said third transistor and saidfourth transistor are N-type transistor.
 4. The cell of claim 1, whereinthe drain of said third transistor is coupled to an electrical zeropoint.
 5. The cell of claim 1, wherein the drain of said fourthtransistor is coupled to an electrical zero point.
 6. The cell of claim1, wherein voltage of said second word line terminal is higher thanvoltage of said first word line terminal when said cell is in stand-byand both said second transistor and said first transistor are P-typetransistors.
 7. The cell of claim 1, wherein gate voltage of said secondtransistor is adjusted to reduce the subthreshold leakage current ofsaid second transistor.
 8. A four-transistors SRAM cell, comprising: afirst gate, wherein a first source and a second drain is closed to saidfirst gate; a second gate, wherein a second source and a second drain isclosed to said first gate; a third gate, wherein a third source and athird drain is closed to said third gate, said third source beingcoupled to said first drain; a fourth gate, wherein a fourth source anda fourth drain is closed to said first gate, said fourth source beingcoupled to said second drain; a first electrical terminal which iscoupled to said first gate; a second electrical terminal which iscoupled to said second gate, wherein said second electrical terminal isindependent on said first electrical terminal; and a third electricalterminal which is coupled to said third gate; a fourth electricalterminal which is coupled to said fourth gate.
 9. The cell of claim 8,wherein said first source, said first drain, said second source and saidsecond drain are P-type doped drains.
 10. The cell of claim 8, whereinsaid third source, said third drain, said fourth source and said fourthdrain are N-type doped drains.
 11. The cell of claim 8, wherein voltageof said second electrical terminal is higher than voltage of said firstelectrical terminal.
 12. The cell of claim 8, further comprises couplingboth said third drain and said fourth drain to an electrical zero point.13. A memory cell, comprising: a first multi-doped region, wherein saidfirst multi-doped region is formed by a plurality of doped regions; asecond multi-doped region, wherein said second multi-doped region isformed by a plurality of doped regions; a first gate which is coupled tosaid first multi-doped region; a second gate which is coupled to bothsaid first multi-doped region and said second multi-doped region; athird gate which is coupled to both said first multi-doped region andsaid second multi-doped region, wherein the interface of said secondgate and said first multi-doped region is located between the interfaceof said first gate and said first multi-doped region and the interfaceof said third gate and said first multi-doped region; and a fourth gatewhich is coupled to said second multi-doped region, wherein theinterface of said third gate and said second multi-doped region islocated between the interface of said second gate and said secondmulti-doped region and the interface of said fourth gate and said secondmulti-doped region.
 14. The memory cell of claim 13, wherein said firstmulti-doped region comprises a N-type doped region and a P-type dopedregion.
 15. The memory cell of claim 13, wherein said second multi-dopedregion comprises a N-type doped region and a P-type doped region. 16.The memory cell of claim 13, wherein said first gate is independent onsaid fourth gate.